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| THURSDAY, June 10, 2004, 8:30 AM - 10:00 AM | Room: 6D |
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TOPIC AREA: NANOMETER ANALYSIS AND SIMULATION
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SESSION 39
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| Issues in Timing Analysis
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| Chair: David Hathaway - IBM Corp., Essex Junction, VT
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| Organizers: Kenneth L. Shepard, Sudhakar Bobba
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| This session considers several issues in the static timing analysis of digital integrated circuits. In the first paper, the effect of power supply variations on timing is analyzed. The second paper offers a statistical gate delay model that considers the effects of multiple input switching. The final paper in this session proposes a new timing analysis algorithm using a two-pass traversal of the timing graph.
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| 39.1 |
Worst-Case Circuit Delay Taking into Account Power Supply Variations
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| Speaker(s): | Dionysios Kouroussis - Univ. of Toronto, Toronto, ON, Canada
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| Author(s): | Dionysios Kouroussis - Univ. of Toronto, Toronto, ON, Canada
Rubil Ahmadi - Univ. of Toronto, Toronto, ON, Canada
Farid N. Najm - Univ. of Toronto, Toronto, ON, Canada
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| 39.2 | Statistical Gate Delay Model Considering Multiple Input Switching |
| Speaker(s): | Aseem B. Agarwal - Univ. of Michigan, Ann Arbor, MI
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| Author(s): | Aseem B. Agarwal - Univ. of Michigan, Ann Arbor, MI
Florentin Dartu - Intel Corp., Hillsboro, OR
David Blaauw - Univ. of Michigan, Ann Arbor, MI
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| 39.3 | Static Timing Analysis Using Backward Signal Propagation |
| Speaker(s): | Dongwoo Lee - Univ. of Michigan, Ann Arbor, MI
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| Author(s): | Dongwoo Lee - Univ. of Michigan, Ann Arbor, MI
Vladimir Zolotov - Motorola, Inc., Austin, TX
David Blaauw - Univ. of Michigan, Ann Arbor, MI
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